1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly, it relates to a method of fabricating a semiconductor device having an insulator film such as a gate insulator film.
2. Description of the Background Art
Following the recently increased density and degree of integration of an ULSI (ultra large scale integrated circuit), elements thereof are also refined. In order to refine the elements, it is important to refine an element isolation region simultaneously with refinement of the elements themselves. Therefore, various methods are proposed for refining the element isolation region. In particular, STI (shallow trench isolation) is proposed in place of the conventional LOCOS (local oxidation of silicon) method.
In a semiconductor device including a MOS transistor, a gate insulator film is formed on the surface of an element forming region of a semiconductor substrate enclosed with an element isolation region. This gate insulator film is generally prepared from a silicon oxide film formed by heat-treating a silicon substrate in an oxidizing atmosphere or a silicon oxynitride film formed by heat-treating the silicon substrate in an oxidizing atmosphere containing nitrogen atoms. In this case, the gate insulator film is generally formed by performing heat treatment at a temperature of about 700° C. to about 850° C. with a low oxidizing velocity in order to excellently control the thickness thereof, as disclosed in Japanese Patent Laying-Open No. 2000-223488, for example. Japanese Patent Laying-Open No. 2000-223488 discloses a technique of forming a gate insulator film by performing oxidation at a temperature of not more than 850° C.
FIGS. 15 to 23 are sectional views for illustrating a conventional fabrication process for a semiconductor device including a MOS transistor. FIG. 24 is a sequence diagram showing conditions for forming a gate insulator film of the conventional MOS transistor. The conventional fabrication process for a semiconductor device is now described with reference to FIGS. 15 to 24.
First, pad oxide films 102 consisting of silicon oxide and silicon nitride films 103 are successively deposited on a silicon substrate 101 and thereafter patterned, as shown in FIG. 15. Thereafter the pad oxide films 102 and the silicon nitride films 103 are employed as masks for etching portions of the silicon substrate 101 for defining element isolation regions, thereby forming trenches (element isolation trenches) 150.
As shown in FIG. 16, heat treatment is performed at a temperature of about 1000° C. to about 1200° C., thereby forming liner oxide films 104 consisting of silicon oxide on the surfaces of the element isolation trenches 150.
As shown in FIG. 17, silicon oxide films 105 are deposited by high-density plasma CVD to fill up the element isolation trenches 150. Thereafter the silicon oxide films 105 are polished/partially removed by CMP (chemical mechanical polishing) through the silicon nitride films 103 serving as stoppers, to be flattened as shown in FIG. 18.
Then, the silicon nitride films 103 are removed by wet etching with phosphoric acid and the pad oxide films 102 are thereafter removed by wet etching with dilute hydrofluoric acid thereby exposing active regions (element forming regions) of the silicon substrate 101, as shown in FIG. 19. When the pad oxide films 102 are removed by wet etching, the upper surfaces and the side surfaces of the silicon oxide films 105 are also etched to some extent. Thus, element isolation films consisting of the silicon oxide films 105 are embedded in the element isolation trenches 150, thereby forming the element isolation regions.
Then, sacrifice oxide films 106 consisting of silicon oxide are formed on the surfaces of the exposed element forming regions, as shown in FIG. 20. An n-type impurity and a p-type impurity are ion-implanted from above the silicon substrate 101 through the sacrifice oxide films 106 respectively, thereby forming an n-type well region 111 and a p-type well region 112. Thereafter the sacrifice oxide films 106 are removed with dilute hydrofluoric acid, thereby exposing the element forming regions of the silicon substrate 101 as shown in FIG. 21.
Then, gate insulator films 107 consisting of silicon oxide are formed on the surfaces of the exposed element forming regions of the silicon substrate 101 by thermal oxidation at a temperature of about 750° C., as shown in FIG. 22. More specifically, temperature increase and temperature reduction steps are carried out in an N2 gas atmosphere while heat treatment is performed in a wet oxidizing atmosphere containing about 50 vol. % of O2 gas and about 50 vol. % of H2 gas respectively under a temperature condition of about 750° C. as shown in FIG. 24, thereby forming the gate insulator films 107 consisting of silicon oxide.
Finally, gate electrodes 108 of polysilicon are formed on the silicon oxide films 105 to come into contact with the upper surfaces of the gate insulator films 107, as shown in FIG. 23. The gate electrodes 108 are employed as masks for ion-implanting impurities, thereby forming a source region (not shown) and a drain region (not shown) in the n-type well region 111 and the p-type well region 112 respectively. An interlayer dielectric film 109 consisting of silicon oxide or silicon nitride is formed to cover the overall surface, and contact holes 109a are thereafter formed in prescribed regions of the interlayer dielectric film 109. Electrodes 110 consisting of an aluminum alloy are formed to be electrically connected with the source region, the drain region and the gate electrodes 108 respectively through the contact holes 109a. Thus, the conventional semiconductor device including a MOS transistor is completed.
In the aforementioned conventional method of fabricating a semiconductor device, oxygen atoms enter between silicon atoms on the interface between the liner oxide films 104 and the silicon substrate 101 in the step of forming the liner oxide films 104 consisting of silicon oxide shown in FIG. 16, to result in cubical expansion. On the interface between the silicon substrate 101 and the liner oxide films 104, therefore, internal stress results from this cubical expansion. Particularly on upper corners 150a of the element isolation trenches 150, upward cubical expansion is inhibited due to the presence of the silicon nitride films 103 serving as oxidation-resistant masks, to result in strong stress. In general, the gate insulator films 107 are formed to cover the upper corners 150a of the element isolation trenches 150, subjected to the strong stress, in the later step of forming the gate insulator films 107 (see FIG. 22). In this case, the gate insulator films 107 consisting of silicon oxide are formed at the low temperature of about 750° C. (about 700° C. to about 850° C.) in the conventional fabrication method, and hence it is difficult to release the upper corners 150a of the element isolation trenches 150 from the strong stress in formation of the gate insulator films 107. Therefore, the gate insulator films 107 formed to cover the upper corner portions 150a of the element isolation trenches 150 subjected to the strong stress are disadvantageously reduced in reliability. In particular, the gate insulator films 107 are reduced in time dependent dielectric breakdown (TDDB) serving as the measure for evaluating the reliability of the gate insulator films 107.